M. Iliopoulos and Th. Antonakopoulos:

Optimized Reconfigurable MAC Processor Architecture

The 8th International IEEE Conference on Electronics, Circuits, and Systems - ICECS 2001, Malta, 2-5 September 2001.

Abstract: Inefficient resources utilization is met in various embedded communication devices, which are based on standard processor cores and custom hardware modules. This paper addresses the inefficient resources utilization problem in MAC processor designs and presents a solution that is based on reconfigurable processor architecture and on dynamic-static instruction partitioning, depending on medium access protocol requirements. The presented instruction partitioning is based on statistical and time critical functional analysis for minimizing the required hardware resources.

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