A. Prodromakis, N. Papandreou, E. Bougioukou, U. Egger, N.
Toulgaridis, Th. Antonakopoulos, H. Pozidis, E. Eleftheriou:
Controller Architecture for Low-latency Access to Phase-Change Memory in OpenPOWER Systems
The International Conference on Field-Programmable Logic and
Applications (FPL), Lausanne, Switzerland, 29th August–2nd September
2016.
Abstract: Novel forms of nonvolatile
memory, such as phase-change memory (PCM), promise low latency and small
granularity of read and write access at high storage density. They also
feature very high endurance. These characteristics make them highly
desirable for emerging high-capacity (hybrid) memory applications such
as in-memory databases and in-memory processing. In this work we present
the architecture, implementation and experimental performance results of
an FPGAbased PCM memory controller for OpenPOWER servers. The memory
controller leverages the Coherent Accelerator Processor Interface (CAPI)
of the POWER processor in order to offer low-latency access to the CPU
memory space. In addition, the memory controller implements an efficient
management protocol that supports a dynamic size of pending read and
write requests in order to offer high bandwidth under mixed-type
workloads. We describe the architecture and implementation details of
the memory controller and we demonstrate its performance using a
prototype platform based on different types of OpenPOWER servers
equipped with CAPI-enabled FPGA cards. The developed PCM controller is
evaluated in terms of sustained data rates (MBps) and access latency (us).
Experimental results are based on legacy commercial 90nm PCM chips as
well as on accurate HW emulation of next generation PCM chips.
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