S. Korkotsides, G. Bikas, E. Eftaxiadis and Th. Antonakopoulos:

BER Analysis of MLC NAND Flash Memories based on an Asymmetric PAM Model

The 6th International Symposium on Communications, Control, and Signal Processing (ISCCSP 2014), May 2014, Athens, Greece.

Abstract: The reliability of multilevel NAND Flash memories, which are used extensively on solid-state drives, is strongly affected by their aging, ie. the number of applied program/erase cycles (P/E). A multilevel memory uses discrete voltage levels to represent the various bit patterns and, at the beginning of the life-time of such a device, these voltage levels demonstrate distributions with very small variances, resulting to very low symbol and bit-error-ratio (BER). As the number of applied P/E cycles increases, the variance of the voltage levels also increases and that results to increased BER. In this paper, we present a general model for four-level NAND Flash memories that can be used to estimate the memories' BER as a function of the used NAND technology and the aging process. For that purpose, we use asymmetric Pulse Amplitude Modulation with data-dependent channel noise and we provide analytic expressions for the behavior of such memories, and we associate their aging with noise conditions and used technology.

If you need additional information concerning this paper, please contact either one of the authors or send an e-mail to: comes-sup@ece.upatras.gr