Th. Antonakopoulos, N. Toulgaridis, M. Varsamou, E. Bougioukou and T. Petropoulos:

An Advanced Flash Emulator for Designing Today’s High-Capacity Controllers

Flash Memory Summit 2018, August 7-9, 2018, Santa Clara, USA.

Abstract: Designing complex NAND flash controllers is a difficult business. Designers must test the logic on something that resembles the final device configuration before it has been fully defined or built. And often the memory ICs are not even available. The usual solution is to use an emulator (often jerry-built or home-grown) to replace the target devices. However, such emulators are typically limited in scope and flexibility and lack the large capacities (hundreds of GB per channel) in actual use today. A new approach employs PCIe-based FPGA boards attached to the PCIe slots of a high-end Xeon server. It uses the server’s DRAM as a huge shared memory that each emulated channel can access independently. The emulator is programmable, supports standard memory interfaces, and can emulate a large memory area (supporting multiple channels). Experimental results show that all timing requirements are satisfied under maximum read/write workloads. High-level software allows the collection and processing of various statistics on the fly.

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